In the integrated circuit and system design industry, a bus protocol is used to control the operation of a bus or a plurality of interconnections between devices and/or integrated circuits. The bus protocol usually directly impacts the systems performance. For example, bus protocols have been designed to perform burst bus cycles. In a burst bus cycle, a base address is provided external to a data processor. In an memory device or latch, which is external to the data processor, a group of bits of the address are latched or stored. Logic or a state machine external to the data processor is used to cycle the latches or memory devices in a manner which manipulates the base address in a sequential fashion to form two or more unique addresses from the single base address. Data corresponding to each of these unique addresses is read from a memory external to the data processor in a manner which is faster than providing the unique addresses individually from the processor.
Unfortunately external counters and glue logic/state machines are difficult to design and difficult to operate with fast-operating microprocessor systems. At very high frequencies, due to the on-to-off chip delays, the formation of external logic signals which control the external counters and glue logic/state machines are slow and address cycling may be impossible to accomplish.
Furthermore, two devices in a system will usually communicate with one another. Therefore, bus protocols usually require some mechanism to acknowledge or terminate a bus transfer initiated by one device to transmit data to a second device. In prior bus protocols, acknowledge signal(s) were required to be valid (i.e. a valid logic one or a valid logic zero) about all clock edges of the system clock. This is cumbersome because at high frequencies, a slave device may not be able to actively assert or deassert an acknowledge signal coupled to a master device before the master device experiences a clock edge. Buses with transmission line effects further enhance this problem.
Therefore, a new bus protocol is required in order to improve upon the disadvantages listed above.